Field of the Invention
The present invention generally relates to digital memory circuits and more specifically to an 8-transistor dual-ported static random access memory (SRAM).
Description of the Related Art
As integrated circuit process technology advances, transistors having smaller dimensions can be fabricated and the density of semiconductor memory devices increases. However, as transistor sizes shrink, the reliability of conventional storage cells is reduced due to variations in the process technology and low operating voltages of the memory devices.
For example, FIG. 1A illustrates a 6-transistor storage cell 100 configured in a memory array, according to the prior art. The 6-transistor storage cell 100 is a conventional static random access memory (SRAM) cell that includes four NMOS (n-type metal oxide semiconductor) transistors and two PMOS (p-type metal oxide semiconductor) transistors. A word line 102, coupled to the gates of two pass transistors, may be enabled to read from or write to a storage circuit formed by cross-coupled inverters. The word line 102 is coupled to many 6-transistor storage cells 100 in a row, but only one row is accessed during a read or write operation. When the word line 102 is asserted (driven to a high voltage or TRUE) to perform a read operation, the bit stored in the storage circuit is transferred to bit line H 105 and the complement is transferred to bit line L 106. A sense amplifier 108 amplifies the difference in voltage levels between bit line H 105 and bit line L 106 and the amplified difference, output 109 is sampled to read the bit stored in the 6-transistor storage cell 100.
As fabricated transistor sizes shrink and operating voltages are reduced, read operations may be unstable when the transistor threshold voltage is too large compared with the operating voltage, leaving little margin for switching. A read disturb fault occurs when the word line 102 is asserted to read a first 6-transistor storage cell 100. As a consequence, the first 6-transistor storage cell 100 or any other 6-transistor storage cell in the row may be inadvertently written when the first 6-transistor storage cell 100 is read. Therefore, the value stored in the second 6-transistor storage cell 100 may be changed (disturbed) during the read of the first 6-transistor storage cell 100.
The read disturb fault results from a transistor mismatch caused when the size of the access transistors coupled to bit line H 105 and bit line L 106 is increased to ensure that the 6-transistor storage cell 100 can be reliably written. Specifically, to successfully write the 6-transistor storage cell 100, the access transistors must be able to overcome the pullup current generated in the PMOS pull-ups and the pulldown current in the pulldowns. On the other hand, for the 6-transistor storage cell 100 to be readable, the access transistors should be small relative to the pulldown transistors. The smaller access transistor sizing maximizes the positive voltage margin needed to guarantee that the value stored in the cell is not flipped during a read operation. Clearly, the two operational modes (read and write) have conflicting goals that present a greater challenge as the process technology shrinks and operating voltages are reduced.
An alternative to the conventional 6-transistor storage cell is an 8-transistor storage cell. FIG. 1B illustrates an 8-transistor storage cell configured in a memory array, according to the prior art. The 8-transistor storage cell 110 is also conventional SRAM cell. The 8-transistor storage cell 110 includes six NMOS transistors and two PMOS transistors and is robust compared with the 6-transistor storage cell 100 because two additional NMOS transistors are used in the 8-transistor storage cell 110 to prevent read disturb faults.
Separate word lines are provided for reading and writing to avoid read disturb faults. More specifically, a word line write 112 is coupled to the gates of two pass transistors. When a write operation is performed the word line write 112 is asserted and the value to be written is driven on bit line write H 115 and the complement of the value is driven on bit line write L 116. When a read operation is performed to read from a first 8-transistor storage cell 110, the bit line read 120 is precharged to a high voltage level, the word line read 114 is asserted, and the value stored in the 8-transistor storage cell 110 is output to the bit line read 120. The additional transistors in the read path prevent the transfer of any signal to the storage circuits of the 8-transistor storage cells 110. Therefore, read disturb faults are prevented.
Although the 8-transistor storage cell 110 is more robust compared with the 6-transistor storage cell, both cells do require precharging of the bit lines for read operations. Furthermore, the bit lines are precharged to a relatively high voltage (typically VDD, the high power supply voltage) so that a difference between a “1” and “0” can be detected. In particular, the bit line read 120 is precharged to a high voltage level and driven to a low voltage level when a “0” is read. The precharge and potential discharge for read operations increase the power consumption of the storage cell compared with an storage cell that does not require a precharge to a high voltage level for each read operation.
While the 8-transistor storage cell 110 does not suffer from read faults, the 8-transistor cell does rely on a precharge to a high voltage level for read operations. Therefore, the 8-transistor storage cell 110 consumes more power compared with the 6-transistor storage cell 100 due to the larger voltage swings that occur on the read bit line 120.
As the foregoing illustrates, what is needed in the art is a storage cell that is designed to reduce the frequency of read disturb faults and is more power efficient than conventional storage cells.